Finfet semiconductor device having local buried oxide

ABSTRACT

There is set forth herein in one embodiment a FinFET semiconductor device having a fin extending from a bulk silicon substrate, wherein there is formed wrapped around a portion of the fin a gate, and wherein proximate a channel area of the fin aligned to the gate there is formed a local buried oxide region aligned to the gate. In one embodiment, the local buried oxide region is formed below a channel area of the fin.

FIELD OF THE INVENTION Background of the Invention

Extremely thin Silicon-On-Insulator (ETSOI) planar Metal Oxide SiliconField Effect Transistors (MOSFETs) are desirable for many aspects. Suchstructures provide fully depleted devices having planar architectureswith superior short channel control, low junction leakage current, andan un-doped body with low variability from random dopant fluctuations.Thin body semiconductor devices have limitations, however, in that theyare not well adapted for stress inducement in the channel (or body) forcarrier mobility enhancement. Also, source/drain resistance tends to betoo high due to thin Silicon (Si) layer (i.e., small amount of Simaterials) for many applications.

In one proposed solution for inducing stress to a channel and reducingsource/drain resistance, the structure of raised sources and drains canbe formed using Si epitaxial growth. However, the added stress in achannel of a MOSFET on ETSOI by using such methods can still be minimaland the source and drain resistance is still too high for manyapplications which typically employ MOSFETs formed on a bulk Sisubstrate.

In contrast to traditional planar metal-oxide-semiconductor,field-effect transistors (MOSFETs), which are fabricated usingconventional lithographic fabrication methods, non-planar FETsincorporate various vertical transistor structures. One suchsemiconductor structure is the “FinFET”, which takes its name from themultiple semiconductor “fins” that are used to form the respective gatechannel with small footprint. Advantageously, the fin structure helps tocontrol current leakage through the transistor in the off state, and adouble gate or tri-gate structure may be employed to control shortchannel effects.

BRIEF SUMMARY

There is set forth herein in one embodiment a FinFET semiconductordevice having a fin extending from a bulk silicon substrate, whereinthere is formed wrapped around a portion of the fin a gate, and whereinproximate a channel area of the fin aligned to the gate there is formeda local buried oxide region aligned to the gate. In one embodiment, thelocal buried oxide region is formed below a channel area of the fin.

BRIEF DESCRIPTION OF SEVERAL VIEWS OF THE DRAWINGS

One or more aspects of the present invention are particularly pointedout and distinctly claimed as examples in the claims at the conclusionof the specification. The foregoing and other objects, features, andadvantages of the invention are apparent from the following detaileddescription taken in conjunction with the accompanying drawings inwhich:

FIG. 1 is a top view of a FinFET semiconductor device having a localburied oxide region.

FIG. 2 is a perspective view of a FinFET semiconductor device having alocal buried oxide region.

FIG. 3 is a perspective view of a FinFET semiconductor device having alocal buried oxide region in another embodiment.

FIG. 4 is a flow diagram illustrating a method including forming a localburied oxide region in a FinFET semiconductor device.

FIGS. 5-12 are fin widthwise cross sectional side view schematicdiagrams illustrating fabrication of a FinFET semiconductor devicehaving a local buried oxide region.

FIGS. 13 and 14 are fin lengthwise cross sectional side view schematicdiagrams illustrating a semiconductor device.

FIG. 15 is a fin lengthwise schematic diagram illustrating asemiconductor device having a plurality of FinFETs.

DETAILED DESCRIPTION

There is set forth herein, as depicted in FIGS. 1 and 2, a fin fieldeffect transistor (FinFET) semiconductor device 100 having a fin 202extending from a bulk silicon substrate 102, wherein there is formedwrapped around a portion of the fin 202 a gate 101, and whereinproximate a channel area 103 of the fin aligned to the gate 101 there isformed a local buried oxide region 104. Between substrate 102 and gate101 there can be disposed oxide 204 (oxide layer 204). Oxide 204 can bedisposed in surrounding relation to a lower elevation portion of fin202. Shown as having a single fin in the embodiment of FIGS. 1 and 2,semiconductor device 100 can have more than one fin. In one embodiment,semiconductor device 100 can be provided by bulk wafer defining aplurality of field effect transistors. In one embodiment, semiconductordevice 100 can be provided by an integrated circuit (IC) defining aplurality of field effect transistors.

FIGS. 1 and 2 show a top plan view and isometric view, respectively, ofa FinFET semiconductor device 100 fabricated on Si substrate 102. Thoughonly one fin is illustrated in FIG. 1 for simplicity, there can bemultiple fins 202 fabricated in parallel with fin 202. Fin 202 canextend upwardly from substrate 102. Each fin 202 of a semiconductordevice 100 can be elongated and can include a rectangular cross sectionas depicted in the views of FIGS. 2-12 herein. In the embodimentillustrated, FinFET semiconductor device 100 includes a gate 101 whichcan be wrapped around the top and sides of a fin 202. A source 105 isdefined at one end of fin 202, and a drain 107 is defined at the otherend of fin 202. Source 105 and drain 107 can be defined on fin 202 anddoped by performing appropriate implantation processes. Appropriateimplantation processes can include e.g., implantation of dopants (n-typeor p-type) for n-type and p-type source and drain of FinFETs. A channel103 can be defined by fin 202 intermediate source 105 and drain 107 at aregion of fin 202 covered by gate 101 and aligned to gate 101. Channel103 can be defined in the fin 202 above local buried oxide region 104,the channel 103 having a first end and a second end, a source 105defined at the first end of the channel 103 and a drain 105 defined atthe second end of the channel 103. In one aspect as set forth herein,channel 103 can be delimited by a local buried oxide region 104 belowthe top surface of fin 202 by a distance in one embodiment of betweenabout 20 nm and 40 nm (this distance being the height of the fin portionthat extends above local buried oxide region 104 being referred to asthe active fin height). Therefore, in one embodiment, current can onlyflow through the portion of the channel of fin 202 above local buriedoxide region 104.

Gate 101 in one embodiment can have a gate stack having multiple layers.The multiple layers can include one or more metal layers and one or moredielectric layers. The one or more metal layers can have, e.g., one ormore layers of titanium nitride (TiN), TiAlC, TaN, aluminum (Al), ortungsten (W). The one or more dielectric layers can have, e.g., one ormore of Si-oxide, Si-nitride, or high-k material (e.g., Hf-oxide).Because gate 101 can have have multiple layers, gate 101 can be referredto a gate stack.

As shown in FIG. 1, a semiconductor device 100 can include a localburied oxide region 104 aligned with a gate 101. A channel 103 can bedefined that is aligned with gate 101 and which can be above localburied oxide region 104. Local buried oxide region 104 can be referredto as “BOX”. Local buried oxide region 104 can be formed in one or moreof bulk Si substrate 102 and fin 202 by implantation of oxygen into fin202 followed by annealing. In the embodiments depicted in FIGS. 1-15herein, local buried oxide region 104 is formed in fin 202 to define achannel 103 above local buried oxide region 104 and an area of fin 202below local buried oxide region 104. BOX 104 can be aligned to gate 101and can have a length less than a length of gate 101 as depicted inFIGS. 1 and 2. BOX 104 can be adapted so that BOX 104 blocks a leakagecurrent path between source 105 and drain 107.

In FIG. 3 there is shown a perspective view of an alternative embodimentof device 100. The “active” channel 103 is above the local buried oxideregion 104. The area of fin 202 below the local buried oxide region 104can provide mechanical stability to the substrate. Thus, the location oflocal buried oxide region 104 can be adjusted toward the surface of Sisubstrate 102, or even half way (e.g., as depicted in the embodimentillustrated in FIG. 15) or mostly submerged into the Si-substrate, sothat the active fin channel height is larger to define a stronger FinFETdevice 100.

An exemplary method for making a FinFET semiconductor device 100 havinga local buried oxide region 104 is set forth in the flow diagram of FIG.4 in connection with FIGS. 5-14. FIGS. 5-12 illustrate cross-sectionalviews of a fin 202 perpendicular to the fin direction (widthwise) andparallel and through the gate 101. FIGS. 13-14 are cross-sectional viewsco-extensive with the fin direction (lengthwise) through gate 101. Inthe views of FIGS. 5-12, two fins are illustrated.

At block 402 (FIG. 4), as depicted in FIGS. 5 and 6, there can beperformed SiN layer deposition. For performance of the SiN layerdeposition at block 402 there can be provided a bulk substrate 102having fins 202 and oxide 204 (oxide layer 204). At block 402 inreference to FIG. 5 the providing can include providing a substrate 102,forming fins 202 and filling oxide 204 between fin 202 and depositingthereon an insulation layer 206. Performance of insulation layerdeposition at block 402 can be accompanied by chemical-mechanicalplanarization (CMP) to provide a flat surface to improve efficiently andaccuracy of ensuing gate pattern lithography processes. In oneembodiment, the insulation layer 206 can be e.g., a silicon nitride(SiN) layer as depicted in FIG. 6. Insulation layer 206, which can beprovided by SiN, can serve as a hard mask. The providing at block 402can alternatively include providing a Si substrate having fins 202 andfilled oxide 204 and depositing thereon insulation layer 206 in otherform, e.g., a Si-oxide layer or a combination of Si-nitride and Si-oxidelayers. The thickness of the insulation layer 206 can be in the range ofabout 10 nm to about 100 nm. The providing at block 402 can also includeshallow trench isolation (STI) and formation. As indicated in FIG. 5,shallow trench isolation (STI) oxide 115 can be formed at block 402. Asdepicted in FIG. 5, STI oxide can be deposited into shallow trenches ofSi substrate 102 to isolate sets of devices of semiconductor device 100.The shallow trenches that are filled with STI oxide in the views ofFIGS. 4-12 are shown as having a depth greater than a depth of oxide 204deposited adjacent to fins 202. In another embodiment shallow trenchesfilled with STI oxide 115 can have a depth less than a depth of oxide204 deposited adjacent to fins 202. In another embodiment, shallowtrenches filled with STI oxide can have a depth equal to a depth ofoxide 204 deposited adjacent to fins 202. The depth of oxide 204 can beregarded as the depth of oxide 204 after recessing of oxide 204 at block422 to be described herein. The providing of STI and formation at block404 can also include providing shallow trench isolation (forming atrench with STI oxide 115) between fins 202 depicted in FIGS. 5-12. Adepth of such intermediate trenches can be less than, greater than, orequal to a depth of trenches (filled with STI oxide 115) depicted inFIGS. 5-12.

At block 406 (FIG. 4), as depicted at FIG. 7, there can be performedgate patterning lithography followed by gate reactive ion etching (ME)to open the gate area 101 a. There can be performed gate patterning forproviding an opening in insulation layer 206 (to allow for oxygen ionimplantation in subsequent step). Gate area 101 a as depicted in FIG. 7can be uncovered by photoresist. In one embodiment, the gate patterningcan include providing a mask, the mask having a two dimensional areapattern that defines a gate area of device 100. Removal of the maskprovided by insulation layer 206 can include, e.g., RIE or wet etching.For example, hot H3PO4 acid can be used to remove nitride 206 withoutdamaging the Si fins 202 and filled oxide 204.

At block 412 (FIG. 4), as depicted in FIG. 8, there can be performedoxygen ion implantation into the exposed gate area 101 a. There can beformed a local buried oxide region 104 (FIG. 9) in fins 202. Forming ofa local buried oxide region 104 (FIG. 9) can be performed by using ionimplantation of oxygen (O⁺) through an exposed surface 202 s of fin 202into an area within fin 202 and followed by thermal annealing. Byperforming implantation of oxygen through a same opening defined by masklayer 206 used for gate patterning, a local buried oxide region 104 canbe regarded as being “self aligned” to gate 101. Local buried oxideregion 104 can be aligned to a gate 101. Local buried oxide region 104can have a length in common with a length of gate 101. In addition or inthe alternative, local buried oxide region 104 can have a width incommon with width of gate 101. In one embodiment, local buried oxideregion 104 can have one or more a length and width less than a lengthand width, respectively, of gate 101. In one embodiment, theimplantation of oxygen ions can be accompanied by implantation of one ormore of nitrogen (N), carbon (C) and fluorine (F). The energy and doseof implantation of one or more of oxygen ions, N, C, and F is designedto form a local buried oxide region 104 (BOX) deep enough underneath thea surface of fin 202, so that dopant diffusion is reduced and stress atlocal buried oxide region 104 and surrounding areas of fin 202 isreduced. The implant energy of O is in the range of from about 10 KeV toabout 100 KeV. In one embodiment, the implant energy of O is in therange from about 200 KeV to about 1 MeV. In one embodiment, the localburied oxide region 104 (shown as formed in FIG. 9) can be formed at alocation of between about 20 nm and about 40 nm beneath the surface 202s of fin 202 (i.e., a thin silicon layer having a thickness of fromabout 20 nm to about 40 nm as similar to the thin Si layer in an ETSOIfor serving as the channel for a MOSFET). In one embodiment, the ionimplantation can include implantation of oxygen (with dose in the rangeof 10¹⁵ to 10¹⁷ cm⁻²) and followed by implantation sequentially ofnitrogen (N), carbon (C), or fluorine (F) with smaller dose (in therange of from about 1.0% to about 3.0% of the main O dose). In oneembodiment, mask 206 defines both an area of implantation of oxygenions, and in a manner set forth herein, a gate area 101 a, an area ofgate electrode material. With use of mask 206 a formed local buriedoxide region 104 can be self aligned to a gate area 101 a andaccordingly can be self aligned to a formed gate 101 when gate 101 isformed. When local buried oxide region 104 is formed a channel area 103a can be formed on fin 202 above local buried oxide region 104.

According to one prior art method for the fabrication of a commerciallyavailable Silicon on Insulator (SOI) substrate, a method known asSeparation by Implantation of Oxygen (SIMOX) can be employed. The SIMOXmethod performs oxygen implant into bulk Si-substrate in blank (i.e., nophotoresist pattern) with high dose (>10¹⁸ cm⁻²) and at elevatedtemperature (>600° C.) during implantation and then followed by a postimplant annealing at high temperature (>1200° C.) to eliminate defectsand re-crystallize the surface, so that a Si-On-Insulator (SOI)substrate is formed. In one method in this disclosure for the formationof a local buried oxide region 104, oxygen implant is performed in alocalized area through a patterned mask 206 and with a lower dosage andno elevated temperature during implantation and also lower annealingtemperature after implantation than in the case of a SIMOX for SOIsubstrate fabrication. According to one embodiment, the oxygenimplantation for the formation of local buried oxide region 104 is at adosage of about 10¹⁶ to 10¹⁷ ions/cm², which is about 1% to about 10% ofthe known blank implant of oxygen at elevated temperature in the SIMOXtechnology method for forming SOI substrate. In one embodiment, theimplant energy of O can be <120 KeV (to achieve the formation of BOX20-40 nm below the active fin). The post implant annealing temperaturein this disclosure is in a range of from about 800° C. to about 1100° C.which is significantly lower than that for the referred to SIMOXprocess.

At block 416 (FIG. 4), as depicted in FIG. 9, there can be performedpost implant high temperature annealing. High temperature annealing atblock 416 can be performed subsequent to implantation of oxygen at block412. The high temperature annealing can be performed e.g., at from about800 deg. C to about 1100 deg. C. in inert ambient to form a local buriedoxide region 104 (BOX) and heal the damage in the silicon channel fromthe implantation at block 412. By comparison, post implantationannealing temperatures seen in SIMOX for SOI substrate fabricationprocesses are in the range of >1200C. The implant of additives (N, C, F)with oxygen ions helps to suppress the generation of defects during postimplant thermal annealing and also lower than the annealing temperaturesignificantly. The implantation of the noted additives (N, C, F) alsoprovides smooth stress transition between the local buried oxide region104 and surrounding Si channel area 103 a (FIG. 11) of fin 202. Thus, apost implant annealing temperature lower than that in SIMOX for SOIsubstrate fabrication can result in a robust “defect free” and minimumstress around the Si channel area 103 a (FIG. 1). Furthermore, inclusionof one or more of the noted additives N, C, and F can suppress dopantsof B, P, diffusion into the local buried oxide region 104 from anadjacent channel area 103 a, so that there is provided reducedfluctuations of device parameters.

At block 422 (FIG. 4), as depicted in FIG. 10, there can be performedlocal oxide recess to expose a sidewall of fins 202. The oxide 204 canbe recessed deep enough to the level of BOX 104 (e.g., to the middle ofBOX level, or at least 10 nm below the top of BOX). In one embodiment,oxide 204 can be recessed to a certain level, the certain level within arange from the top of BOX 104 to a bottom of BOX 104. A thin oxide(e.g., SiO₂) layer 1103 (i.e., an interfacial layer) can be grown on asurface of fin 202 as depicted in FIG. 9 after the oxide recess forrevealing the fin. The oxide layer 1103 can be used as the gatedielectric in a gate first process or oxide layer 1103 can be used as adummy gate dielectric in a gate last process. In one embodiment, a gatedielectric of gate 101 can be a multiple layer of thin Si-oxide,Si-oxynitride, and high-k (HfO2) materials to achieve high quality andthin effective thickness and low leakage.

At block 428 (FIG. 4) as depicted in FIG. 11 there can be performedpolysilicon deposition. The polysilicon deposition can be performed onan entire wafer. A thickness of the polysilicon layer 2101 can be thickenough so that a gate area 101 a is fully filled with polysilicon.

At block 432 (FIG. 4), as depicted in FIG. 12, there can be performedchemical-mechanical planarization (CMP) to planarize the gate stack andinsulation layer 206 which can be provided by SiN. The polysilicon gateheight can be controlled by a thickness of insulation layer 206, and thegate height can be above the top of fin 202 by between about 20 nm andabout 40 nm. Planarization can improve efficiency and accuracy ofensuing processing.

At block 436 (FIG. 4), as depicted in FIG. 13, there can be performedremoval of insulation layer 206 which can be provided by SiN. FIG. 13 isa fin lengthwise cross sectional side view of the semiconductor device100 depicted in the fin widthwise cross sectional views of FIGS. 5-12.The removal can be performed using hot phosphorus acid which isselective to silicon and oxide. In one aspect, only insulation layer 206is removed. With insulation layer 206 removed (FIG. 12), the non-channelportion of fins 202 are exposed for further process steps to formcomponents, e.g., spacers, source/drain, contacts to complete the FinFET(as a poly-gate process) in accordance with a gate first process. Wherea FinFET device 100 is completed using a “gate first” processpolysilicon layer 2101 can define a gate electrode 101 e (FIG. 14).

Alternatively, at block 440 (FIG. 4) there can be performed completionof a FinFET device 100 by a gate last process (with the poly gate stackto be removed later in process steps). According to a gate last process,a poly-Si layer 2101 can be used as a temporary gate stack to form anoffset spacer, followed by optional Halo implantation and extensionimplantations. Rapid Thermal Analysis (RTA) can be performed and isoptional depending on a specific integration scheme used. Source anddrain formation can be the same as that in bulk flow with eSiGe (forPFET stress booster), SMT or SiC (for NFET stress booster). There canthen be performed Interlayer Dielectric (ILD) formation, metal gateformation, Middle of Line (MOL) formation silicate formation and contactformation.

Further aspects of a FinFET semiconductor device having a local buriedoxide region 104 are now described with reference to FIGS. 1-3 and FIGS.14-16. It is seen with reference to FIGS. 1-3 and FIGS. 14-16 that localburied oxide region 104 can be formed only under the gate 101 and a wellcontrolled channel 103 but not under a source and drain 105 and 107.Such local buried oxide region 104 underneath a defined channel 103 caneffectively eliminate or block the leakage current between the source105 and drain 107 (i.e., similar to the advantage exhibited as in thecase of a MOSFET fabricated on SOI substrate, e.g., ETSOI device). Theactive channel 103 is above the BOX 104 and the active fin height isdetermined by the energy/dose level of the oxygen implantation. Inaddition or alternatively the depth of channel 103 can be controlled byone or more of varying a dosage of oxygen ion implantation and theinclusion of zero or more additives with the implantation. Channel 103can be aligned to gate 101 and local buried oxide region 104 can bealigned to gate 101. Accordingly, local buried oxide region 104 can bealigned to channel 103 and channel 103 can be aligned to local buriedoxide region 104.

In the view of FIG. 14 there is depicted a gate 101 provided by a gatestack having gate electrode 101 e and gate dielectric 101 d. Whensemiconductor device 100 is fabricated by a gate first process a gateelectrode 101 e can be provided by polysilicon layer 2101 and gatedielectric 101 d can be provided by oxide layer 1103. While gateelectrode 101 e and gate dielectric 101 d are set forth herein in oneembodiment as having a single layer each, gate electrode 101 e and gatedielectric 101 d can include one or more layers. In one example gateelectrode 101 e can include multiple conducting layers, e.g., TiN, TaN,TiAl, TiC, Al, and W, (e.g., to set the correct “work function” inadvanced CMOS technology nodes). Also, the gate dielectric 101 d mayalso be multiple layers of dielectric, e.g., high-k and SiO₂, for bettercapacitive coupling to channel 103 and smaller leakage between the gateelectrode 101 e and channel 103. The combination of one or more layersof a gate electrode and one or more layers of a gate dielectric can beregarded as a “gate stack”. As illustrated in FIG. 14, local buriedoxide region 104 can be aligned with gate 101. Gate 101 can be boundedby imaginary vertically extending planes 101 p that extendperpendicularly through substrate 102. In one embodiment, local buriedoxide region 104 can be formed so that it does not extend lengthwise ineither direction beyond the imaginary vertically extending planes 101 p.In one embodiment, local buried oxide region 104 can be aligned to gate101 by having at least a portion thereof within a location delimited byplanes 101 p. In one embodiment, local buried oxide region 104 can bealigned to gate 101 by being defined within a location delimited byplanes 101 p and by being absent of a portion that extends external to alocation delimited by planes 101 p. In one embodiment, local buriedoxide region 104 can be aligned to gate 101 by being defined within alocation delimited by planes 101 p, by being absent of a portion thatextends external to a location delimited by planes 101 p, and by havinga length in common with a length of gate 101. By providing local buriedoxide 104 with use of mask 206 to be self aligned to gate area 101 a andgate 101 when formed, local buried oxide region is aligned to gate area101 a and gate 101 when formed.

In one embodiment, channel 103 can be aligned to gate 101 by having atleast a portion thereof within a location delimited by planes 101 p. Inone embodiment, channel 103 can be aligned to gate 101 by being definedwithin a location delimited by planes 101 p and by being absent of aportion that extends external to a location delimited by planes 101 p.As depicted in the views of FIGS. 1-15, a gate 101 can be disposed overa fin 202 having defined therein a BOX 104 aligned to gate 101 and achannel 103 aligned to gate 101. In one embodiment, a gate 101 disposedover fin 202 can include a portion within an area delimited by imaginaryvertically extending planes 101 f (depicted in FIG. 12) that boundsidewalls of fin 202 and extend perpendicularly to substrate 102 (whichcan be planar) and a portion external to an area delimited by imaginaryvertically extending planes 101 f bounded by sidewalls of fin 202. Inone embodiment, a gate 101 disposed over fin 202 can be entirely definedwithin an area delimited by imaginary vertically extending planes 101 f(depicted in FIG. 12) that bound sidewalls of fin 202 and extendperpendicularly to substrate 102 (which can be planar) and can be absenta portion external to an area delimited by imaginary verticallyextending planes 101 f bounded by sidewalls of fin 202. In FIGS. 13-15dotted line 2502 indicates an elevation of a base of fins 202, i.e., thedepth to which bulk substrate 102, e.g., Si, can be recessed to definefins 202.

The providing of a local buried oxide region 104 aligned to a gate 101provides numerous advantages. For example, a field effect channel withsuch a structure is a thin silicon body partially delimited by the localburied oxide region 104 and thus can achieve the leakage currentinhibiting performance on the order of that seen with an extremely thinsilicon insulator (ETSOI) device. With source and drain 105 and 107formed on fins 202 that are formed contiguous with bulk siliconsubstrate 102 as depicted in the views of FIGS. 1-3 and FIGS. 14-15, theheat generated in logic circuits operating at high frequency can bereadily dissipated to bulk silicon substrate 102 to exhibit the sameadvantages as are exhibited by logic circuits fabricated on a bulksilicon substrate.

In one embodiment, as illustrated in FIG. 14, source and drain 105 and107 can be formed to be “embedded” source and drain 105 and 107.Referring to the view of FIG. 14, FIG. 14 is a fin lengthwise crosssectional side view illustrating additional aspects of a method setforth with reference to FIGS. 5-13, wherein the embodiment illustratedin the view of FIG. 14 is depicted as including optional halo implantsand extension implants. Source 105 and drain 107 can be fabricated asembedded sources and drains including stressors. In one embodiment,embedded source and drain 105 and 107 can be fabricated by recessing ofS/D Si, then epi regrowth of SiGe for p-type S/D and SiC for n-type S/Dselectively in order to induce stress in the channel 103. In theembodiment of FIG. 14 (as well as in the embodiment depicted in FIG. 3)source 105 includes epitaxial growth formation 105ep for inducing stressin channel 103 and drain 107 includes an epitaxial growth formation107ep for inducing stress in channel 103.

Further referring to the embodiment depicted in FIG. 14, device 100 isdepicted as having halo implants 106, and source and drain extensionimplants 109 as optional features. As similar to planar CMOS, theseoptional Halo implants 106 and extension implants 109 for FinFETs areuseful in case of short channel length (e.g. <20 nm) for reducing shortchannel effect. Halo implants through the source/drain can alsofacilitate adjustment of the threshold voltage (Vt) of the device 100for implementation of a multi-Vt scheme in logic circuits.

In FIG. 15 there is depicted a semiconductor device 100 having aplurality of FinFETs. Semiconductor device 100 as depicted in FIG. 15includes a first FinFET at location “A” and a second FinFET at location“B”. Each of the first FinFET and second FinFET can be as fabricatedaccording to method in accordance with that described with reference toFIGS. 5-14 except each of the first FinFET at location “A” and thesecond FinFET at location “B” can be absent of halo implants 106 andsource/drain extension implants 109. In one embodiment, FIG. 15 depictsa bulk silicon wafer. In one embodiment, FIG. 15 depicts an integratedcircuit (IC).

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the invention. Asused herein, the singular forms “a”, “an” and “the” are intended toinclude the plural forms as well, unless the context clearly indicatesotherwise. It will be further understood that the terms “comprise” (andany form of comprise, such as “comprises” and “comprising”), “have” (andany form of have, such as “has” and “having”), “include” (and any formof include, such as “includes” and “including”), and “contain” (and anyform contain, such as “contains” and “containing”) are open-endedlinking verbs. As a result, a method or device that “comprises”, “has”,“includes” or “contains” one or more steps or elements possesses thoseone or more steps or elements, but is not limited to possessing onlythose one or more steps or elements. Likewise, a step of a method or anelement of a device that “comprises”, “has”, “includes” or “contains”one or more features possesses those one or more features, but is notlimited to possessing only those one or more features. Furthermore, adevice or structure that is configured in a certain way is configured inat least that way, but may also be configured in ways that are notlisted.

The corresponding structures, materials, acts, and equivalents of allmeans or step plus function elements in the claims below, if any, areintended to include any structure, material, or act for performing thefunction in combination with other claimed elements as specificallyclaimed. The description of the present invention has been presented forpurposes of illustration and description, but is not intended to beexhaustive or limited to the invention in the form disclosed. Manymodifications and variations will be apparent to those of ordinary skillin the art without departing from the scope and spirit of the invention.The embodiment was chosen and described in order to best explain theprinciples of one or more aspects of the invention and the practicalapplication, and to enable others of ordinary skill in the art tounderstand one or more aspects of the invention for various embodimentswith various modifications as are suited to the particular usecontemplated.

1. A method comprising: forming a substrate having a fin extendingtherefrom, said fin being contiguous with the substrate; forming a localburied oxide region in the fin; forming a gate, wherein the local buriedoxide region is under the gate; defining a channel in the fin above thelocal buried oxide region, the channel being aligned to the gate andhaving a first end and a second end; forming a source at the first endof the channel; and forming a drain at the second end of the channel. 2.The method of claim 1, wherein one or more of the source includes anextension.
 3. The method of claim 1, wherein the source includes meansfor reducing a short channel effect.
 4. The method of claim 3, whereinthe means for reducing a short channel effect includes a sourceextension implant.
 5. The method of claim 1, wherein the local buriedoxide region is at least partially formed in the fin.
 6. The method ofclaim 1, wherein the local buried oxide region is entirely formed in thefin.
 7. The method of claim 1, wherein the local buried oxide region ispartially formed in the fin and partially formed in the substrate. 8.The method of claim 1, wherein an area of the substrate below anelevation of a base of the fin includes an area of the local buriedoxide region.
 9. The method of claim 1, wherein the semiconductor deviceis a silicon wafer having a plurality of fins extending upwardly fromthe substrate, wherein fins of the plurality of fins have formed thereinlocal buried oxide regions.
 10. The method of claim 1, wherein thechannel is aligned to the gate.
 11. The method of claim 1, wherein oneor more of the source and drain comprises an epitaxial growth formation.12. The method of claim 1, wherein each of the source and draincomprises an epitaxial growth formation.
 13. The method of claim 1,wherein the source includes means for inducing stress in the channel.14. A method comprising: forming a local buried oxide region in a finextending contiguous from a substrate; and fabricating a gate, whereinthe fabricating is performed so that the local buried oxide region isunder the gate.
 15. The method of claim 14, wherein the forming includesion implantation of oxygen.
 16. The method of claim 14, wherein theforming includes ion implantation of oxygen with one or more of N, C andF.
 17. The method of claim 14, wherein the fabricating includes using agate first fabrication process.
 18. The method of claim 14, wherein thefabricating includes using a gate last fabrication process.
 19. Themethod of claim 14, wherein the forming includes forming the buriedoxide region so that the local buried oxide region is entirely formed inthe fin.
 20. A method comprising: forming a substrate having a fincontiguous with the substrate extending therefrom; forming a localburied oxide region; forming a gate aligned with the local buried oxideregion; defining a channel in the fin, the channel being aligned to thegate and having a first end and a second end; defining a source at thefirst end of the channel; and defining a drain at the second end of thechannel, wherein the local buried oxide region is at least partiallyformed in the fin, and wherein the local buried oxide region is formedunder the gate but not under the source or drain.